• Summer 2026

  Circuit Design Intern — DRAM Design Lab, Samsung

  San Jose, CA

  Designed a fully integrated voltage regulator for the LPDDR6 Built-of-Test (LP6BOT) chip, and a three-path regulation architecture (feedback, PSR feedforward, transient feedforward) achieving >20 dB PSRR at 100 MHz. Coordinated the chip power delivery network layout in Samsung 14nm CMOS.

• Summer 2025

  Graduate Technical Intern — Intel

  Hillsboro, OR

  Developed SPICE/Verilog-A models for adaptive clocking, clock throttling, and switched-capacitor load balancing; created a critical-path replica circuit with background calibration for setup violation detection in Intel 16nm CMOS.

• Summer 2022

  Mixed-Signal Design Engineer Intern — Ambarella

  Santa Clara, CA

  Performed low-power standard-cell schematic and layout design in Samsung 4nm FinFET, and developed an automated Python-based .lib generation flow for digital place-and-route.

• 2020–2021

  Analog and System IC Engineer — Chip Dance Technology

  Shanghai, China

  Led a True Wireless Stereo lithium battery charging chip architecture, taped out in GF 180nm. Designed a sub-threshold BGR with digital trimming DAC and a PVT-tolerant hysteresis comparator, and an LDO-based linear battery charger for 5V-to-4.2V regulation (first inventor on related patent).

Teaching

• Teaching Assistant, Modern Power Management IC Design (ELEN 6920) — Fall 2022 / 2023 / 2024
• Teaching Assistant, VLSI Design Lab (ELEN 6350) — Spring 2025