Experience
Education & Work
Columbia University
Circuit Design Intern — DRAM Design Lab, Samsung
Designed a fully integrated voltage regulator for the LPDDR6 Built-of-Test (LP6BOT) chip, and a three-path regulation architecture (feedback, PSR feedforward, transient feedforward) achieving >20 dB PSRR at 100 MHz. Coordinated the chip power delivery network layout in Samsung 14nm CMOS.
Graduate Technical Intern — Intel
Developed SPICE/Verilog-A models for adaptive clocking, clock throttling, and switched-capacitor load balancing; created a critical-path replica circuit with background calibration for setup violation detection in Intel 16nm CMOS.
Mixed-Signal Design Engineer Intern — Ambarella
Performed low-power standard-cell schematic and layout design in Samsung 4nm FinFET, and developed an automated Python-based .lib generation flow for digital place-and-route.
Chip Dance Technology
Led a True Wireless Stereo lithium battery charging chip architecture, taped out in GF 180nm. Designed a sub-threshold BGR with digital trimming DAC and a PVT-tolerant hysteresis comparator, and an LDO-based linear battery charger for 5V-to-4.2V regulation (first inventor on related patent).
CDUESTC
Teaching
- Teaching Assistant, Modern Power Management IC Design (ELEN 6920) — Fall 2022 / 2023 / 2024
- Teaching Assistant, VLSI Design Lab (ELEN 6350) — Spring 2025
- Substitute Lecturer, Advanced Digital Electronic Circuits (EE6321) — interconnect in VLSI, Spring 2026
Journey
Zigong → Chengdu → Suzhou → Shanghai → New York → San Jose.
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29.35°N, 104.78°E
Zigong
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30.66°N, 104.07°E
Chengdu
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31.30°N, 120.62°E
Suzhou
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31.23°N, 121.47°E
Shanghai
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40.71°N, 74.01°W
New York
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37.34°N, 121.89°W
San Jose