Designing a CSCR-based mismatch compensator for stacked voltage-domain systems, with automatic source/sink mode selection to maintain high efficiency under large current mismatch.
Built a DRAMSim3/Accel-Sim–based framework to analyze per-channel power, latency, and current mismatch in HBM2/HBM3 systems under GPU workloads. Proposed a voltage-stacked HBM power delivery architecture and load-mismatch metrics, identifying up to 113 mA of inter-channel current mismatch and evaluating TSV / power-efficiency trade-offs.
Invented a bidirectional zero-current detector (Bi-ZCD) for source/sink current regulation in voltage-stacked systems, achieving 98.5% peak efficiency and 82% efficiency under 360 mA load mismatch.
→ Published as VSIMO, IEEE VLSI Symposium 2026
Designed a DLDO-assisted buck converter with one-step computational droop compensation and DLDO-controlled current handover, achieving 68-mV droop, 112-ns settling time, and 95.5% peak efficiency for 1A/0.8ns load transients.
→ Published in IEEE SSCL 2025
Designed a rising-edge computational DLDO with load-dependent feedback and DVS computation, achieving a 0.15-ps FoM, 25-mV/ns DVS rate, and low ripple across a 1-to-1050 mA load range.
→ Published at IEEE VLSI Symposium 2026; invited manuscript, IEEE JSSC 2027
Established an analytical model of dynamic load regulation for commonly used DLDO architectures, analyzing the impact of design parameters and providing optimal design points for power switch sizing.
→ Published in IEEE TVLSI 2024
Designed a 9-setting programmable-gain amplifier using replica-based common-mode feedback, and developed the strong-arm comparator, track-and-hold, and capacitor-based DAC for a 125 kHz 8-bit SAR ADC.